Chip designs are sensitive to noise since there is a risk that potential noise generators, such as but not limited to the power grid which provides Vdd and ground signals, will exceed whichever noise-margins were built into the design. On-chip decoupling capacitors (decaps) attached to a power mesh to decrease noise effects are known. Adding decaps is efficient in noise reduction as they provide charge localization. dcaps may be added to areas or regions of an integrated circuit that otherwise have no cells or to “high-risk” areas such as high speed memories.
Placement of decoupling capacitors e.g. for Very Large Scale Integrated Chips (VLSI), is known. Conventional technologies therefor are described inter alia in the following patents: U.S. Pat. Nos. 6,323,050, 6,763,509, 6,898,769, 7,222,320, 7,245,516, 8,421,205, 8,479,136, 9,262,572, 9,465,899, and published patent applications US20070061769A1, US20140167815A1, US20150186586A1 and US20160117431A1.
U.S. Pat. No. 8,224,601 describes decap estimation generally and methods to determine how many decap cells are needed to address a power noise violation created locally in the design.
Another conventional decap (aka dcap) placement process is described in the following public domain document available on Internet: “Decoupling Capacitance Estimation, Implementation, and Verification: A Practical Approach for Deep Submicron SoCs” by David Stringfellow and John Pedicone at Synopsys.com. The document characterizes dynamic variations in supply voltage as a problem which impacts chip performance hence constitutes “a major issue” for DSM SoC design teams. To achieve an acceptable level of voltage fluctuation in the power supply network, a sufficient amount of decoupling capacitance is allocated. Then the resulting decoupling capacitors can act as local charge reservoirs for high-frequency circuits, reducing the effects of power-supply noise on neighboring circuits. The document describes how DCAP estimation and Implementation Flow is used in state of the art VLSI devices.
A state-of-the-art ‘placed and routed’ design methodology is described in “Smart Decap Insertion Methodology” by Amit Dey, Vikas Garg, Rahul Saxena, Shailesh Kumar, available on the web at the following www location: design-reuse.com/articles/31663/smart-decap-insertion-methodology.html. Dey et al describe that “[i]n a ‘placed and routed’ design where decaps and fillers are already inserted, to increase the decap value we have to exchange already inserted fillers into decaps. To enable this m1 and via1 layer have to rerouted which can create potential shorts and spacing violation with m1 of decap when decap is inserted. To reroute the m1 and via1 routes, routing blockages of m1 and via1 layer are added . . . . But before this we remove all the decaps and fillers from the design. After adding the routing blockages there will be numerous shorts and spacing violation between m1 and via1 layers and the routing blockages. To resolve these shorts the routes creating the violation are eco routed, which causes the routes to reposition between the routing blockage . . . . Then the routing blockages are deleted. Now the decaps can easily be inserted without any drc violation, as the m1 layer in decap are occupied in the region of previously added routing blockages. By this technique we get 10-20% improvement in decap value.”
Conventional Place and Route Tools perform Dcap Insertion inter alia. Examples of such software tools include: Synopsys ICC and ICC2, Synopsys Apollo, Cadence Encounter platform, Mentor Graphics—Nitro-SoC, Mentor Graphics—Olympus-SoC and Ansys—Apache RedHawk. At least some of the conventional Place and Route tools mentioned above perform timing-aware aka timing driven placement of std-cells.
Conventional custom TCL scripts able to perform Filler to Dcap swaps have been developed by IBM, Intel, Marvel, QCOM, BroadCom inter alia.
The disclosures of all publications and patent documents mentioned in the specification, and of the publications and patent documents cited therein directly or indirectly, are hereby incorporated by reference. Materiality of such publications and patent documents to patentability is not conceded.